Abstract:In order to solve the high expenditure of special license authorization for commercial central processing unit (CPU) and the improving performance of convolutional neural networks (CNNs), a configurable CNN accelerator was proposed based on multi-view parallelism. And it constructed the system on chip (SoC) with RISC?V (Reduced instruction set computing). Firstly, a set of interfaces incorporated control access bus and data access bus were expanded for high-speed accelerators. Secondly, each operation unit for CNNs was implemented by both multi-view parallelism and structure multiplexing. The hardware circuit structure for convolution unit would be affected by the different combination of view parallelism, thus multi-view parallelism was accomplished by reusing the basic arithmetic structure. The pooling unit was composed of row pooling and column pooling submodules, and which shared the structure of row pooling operation. For the fully connected, a method that parameters could be processed was employed to adapt to the hardware structure of convolution unit, thereby completing reuse between models. Then, different registers were designed for the hardware structure of different computing units, and combined with the open source RISC?V processor to realize multiple CNN models. Finally, different operation units, such as convolution, pooling and fully connected models, were respectively deployed on different platforms to calculate the latency, throughput and speedup ratio. The experimental results demonstrated that the speedup ratio of the same convolution structure on the designed accelerator and CPU platform was 189. The convolution operation of Visual Geometry Group was deployed in the designed accelerator, and the throughput could reach 178.6 GOPS. To sum up, an acceleration effect could be realized by multi-view parallelism, and different CNN models was able to be implemented by configuring registers.