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工程科学与技术:2010,42(2):188-194
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自偏置自适应电荷泵锁相环
(1.西安微电子技术研究所, 陕西 西安 710054;2.西北工业大学 计算机学院,陕西 西安 710072;3.西安电子科技大学 电子工程学院;4.西安微电子技术研究所)
Self-biased Charge Pump PLL with Adaptive Bandwidth
(1.Xi’an Microelectronics Technol. Inst.,Xi′an 710054,China;2.School of Computer, Northwestern Polytechnical Univ., Xi′an 710072, China;3.School of Electronics Eng., Xidian Univ.;4.Xi’an Microelectronics Technol. Inst.)
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投稿时间:2009-02-22    修订日期:2009-04-22
中文摘要: 针对电荷泵锁相环的带宽受限问题,提出带宽随锁相环状态动态变化的自偏置自适应电荷泵锁相环。使锁相环的最大可用带宽与参考信号的频率成线性关系,消除环路带宽受最小参考信号频率的限制,并且使其与工艺、电压和温度无关。根据环路的工作状态动态调节系统的带宽,在提高锁相环锁定速度的同时改善输出信号的噪声性能。采用0.18 μm 1.8 V 1P6M N阱标准CMOS数字工艺完成设计,版图面积为0.048 mm2。仿真结果表明,当参考信号在2.8 MHz到26.6 MHz的范围内变化时,输出信号的相对抖动峰峰值小于1.6 %,工艺、电压和温度对相对抖动的影响小于2.1 %,所有情况下的功耗都小于20 mW。
Abstract:Aiming at the problem that the restrictive bandwidth of the charge pump phase locked loop is restrictive, the self-biased charge pump phase locked loop with adaptive bandwidth whose bandwidth was modified dynamically according to the loop state was proposed. The maximal available bandwidth was proportional to the reference frequency and the restrain of the minimal reference frequency on the loop bandwidth was eliminated. The bandwidth was immune to the variation of the process, voltage and temperature. The loop bandwidth was modified according to the state of the loop, the noise of the output was reduced and the locking speed was improved. The standard of 0.18μm 1.8 V 1P6M CMOS logic process with N trap was used and the layout was 0.048 mm2. Experiment showed that the relative peak-peak jitter was less than 1.6 % when the reference frequency was from 2.8 MHz to 26.6 MHz. The power was less than 20 mW when the variations of process, voltage and temperature were less than 2.1 %.
文章编号:200900133     中图分类号:    文献标志码:
基金项目:国家863计划资助项目(2007aa010402);国家自然科学基金资助项目(60573101)
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引用文本:
魏建军,李春昌,康继昌.自偏置自适应电荷泵锁相环[J].工程科学与技术,2010,42(2):188-194.
Wei Jianjun,Li Chunchang,Kang Jichang.Self-biased Charge Pump PLL with Adaptive Bandwidth[J].Advanced Engineering Sciences,2010,42(2):188-194.