Abstract:Due to the unavailability of fault-free test response corresponding to test pattern which does not belong to test set of IP core, the fault-free signature of Intellectual Property (IP) cores under pseudorandom test is unknown to test developers. Such circumstance poses one of test challenges to IP cores. MSCBIST, one hardware implementation methodology of Built-In-Self-Test (BIST) applicable to digital IP cores was studied based on the principle of multiple signature checking. Fault aliasing probability of multiple signature comparison was analyzed and its approximate value was estimated. By performing on-chip multiple intermediate signature checking, detection latency is decreased significantly. MSCBIST supports parallel signature check without storing multiple fault-free signature on a chip and allows testing and signature comparison to occur concurrently. It was showed that such a test method gives rise to significant improvements in test application time and aliasing probability during functional testing. MSCBIST is applicable both to deterministic test and to pseudorandom test of digital IP cores.